DK-DEV-5SGXEA7N【PDF 280/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51012

2014.01.10

Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing

10-9

To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable

the circuitry permanently with pin connections as listed in the following table.

Table 10-4: Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Stratix V Devices

JTAG Pins

(23)

Connection for Disabling

TMS

TCK

TDI

TDO

V CCPD supply of Bank 3A

GND

V CCPD supply of Bank 3A

Leave open

Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing

Consider the following guidelines when you perform BST with IEEE Std. 1149.1 devices:

? If the “ 10... ” pattern does not shift out of the instruction register through the TDO pin during the first

clock cycle of the SHIFT_IR state, the TAP controller did not reach the proper state. To solve this problem,

try one of the following procedures:

? Verify that the TAP controller has reached the SHIFT_IR state correctly. To advance the TAP controller

to the SHIFT_IR state, return to the RESET state and send the 01100 code to the TMS pin.

? Check the connections to the VCC , GND , JTAG , and dedicated configuration pins on the device.

? Perform a SAMPLE/PRELOAD test cycle before the first EXTEST test cycle to ensure that known data is

present at the device pins when you enter EXTEST mode. If the OEJ update register contains 0, the data

in the OUTJ update register is driven out. The state must be known and correct to avoid contention with

other devices in the system.

? Do not perform EXTEST testing during in-circuit reconfiguration because EXTEST is not supported during

in-circuit reconfiguration. To perform testing, wait for the configuration to complete or issue the

CONFIG_IO instruction to interrupt configuration.

? After configuration, you cannot test any pins in a differential pin pair. To perform BST after configuration,

edit and redefine the BSC group that correspond to these differential pin pairs as an internal cell.

Related Information

IEEE 1149.6 BSDL Files

Provides more information about BSC group definitions.

IEEE Std. 1149.1 Boundary-Scan Register

The boundary-scan register is a large serial shift register that uses the TDI pin as an input and the TDO pin

as an output. The boundary-scan register consists of 3-bit peripheral elements that are associated with

Stratix V I/O pins. You can use the boundary-scan register to test external pin connections or to capture

internal data.

(23)

The JTAG pins are dedicated. Software option is not available to disable JTAG in Stratix V devices.

JTAG Boundary-Scan Testing in Stratix V Devices

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